1. Field of the Invention
The present invention relates to a semiconductor device and a method for the manufacture thereof. More specifically, the present invention relates to the improvement of latch-up resistance of Bi-CMOS integrated circuits.
2. Description of the Background Art
A Bi-CMOS integrated circuit, in which bipolar transistors and CMOS transistors are formed on a single substrate, has been manufactured.
In recent years, techniques for reducing the size of Bi-CMOS integrated circuits, in particular, techniques for reducing the size of bipolar transistors have been proposed. For example, in order to solve the problem of high occupying ratio of element isolation region in the area where bipolar transistors are formed, there have been proposed a large number of techniques for reducing the size of Bi-CMOS integrated circuits by element isolation using trench forming techniques. However, since trench forming techniques have problems of technical difficulties or manufacturing costs, separation techniques by junction forming have still been used.
A conventional semiconductor device and a method for the manufacture thereof will be described below.
First, a conventional semiconductor device (Bi-CMOS integrated circuit) will be described. FIGS. 23 and 24 are cross-sectional views for illustrating a conventional semiconductor device. Specifically, FIG. 23 shows a first island region in which a p-type diffusion resistor element is formed, a second island region in which an npn transistor is formed, and an element isolation region for isolating these island regions in a conventional Bi-CMOS integrated circuit. FIG. 24 shows a third island region in which a CMOS transistor is formed in a conventional Bi-CMOS integrated circuit.
In FIGS. 23 and 24, the reference numeral 1 represents a p-type silicon substrate, 2 represents an n-type buried diffusion layer, 3 represents a p-type first high-concentration isolation diffusion layer formed in the silicon substrate 1 and for isolating lower layer (deep layer) elements, and 4 represents an n-type epitaxial layer.
The reference numeral 5a represents a p-type low-concentration isolation diffusion layer formed in the epitaxial layer 4 and for isolating upper layer elements. The reference numeral 5b represents a p-type well region, which is formed in a third island region C of the epitaxial layer 4 simultaneously with the low-concentration isolation diffusion layer 5a, and in which an NMOS transistor is formed. The reference numeral 6 represents an n-type well region, which is formed in the third island region C, and in which a PMOS transistor is formed.
The reference numeral 7 represents gate electrodes of the MOS transistors, 8a represents an n-type diffusion region constituting an electrode forming region, 8b represents an n-type diffusion region constituting the bipolar transistor, 8c represents an n-type diffusion region constituting the source-drain region of the NMOS transistor, 9a represents a p-type diffusion region constituting a p-type diffused resistor element, 9b represents a p-type diffusion region constituting the bipolar transistor, 9c represents a p-type diffusion region constituting the source-drain region of the PMOS transistor, and 11 represents a field insulating film.
The reference symbol A represents an n-type first island region, B represents an n-type second island region, C represents a third island region, and Q1, Q2, Q3, and Q4 represent parasitic transistors.
As shown in FIGS. 23 and 24, the epitaxial layer 4 is separated into a plurality of island regions A, B, and C by the low-concentration isolation diffusion layer 5a and the first high-concentration isolation diffusion layer 3 formed in the element-isolation region. The n-type diffusion region 8b is fixed to the normal (ON) potential Vcc. The p-type silicon substrate 1 is fixed to GND (not shown).
Next, a method for manufacturing the above-described semiconductor device will be described below. FIGS. 25 to 29 are cross-sectional views for illustrating a conventional method for manufacturing a semiconductor device.
First, as FIG. 25 shows, a silicon oxide film 100 is formed on a p-type silicon substrate 1. Next, the silicon oxide film 100 is patterned. Then, an n-type impurity is implanted using the silicon oxide film 100 as a mask (hard mask), and the substrate 1 is subjected to annealing (heat treatment). Then the silicon oxide film 100 is removed. Thereby, an n-type buried diffusion layer 2 is formed.
Next, as shown in FIG. 26, a silicon oxide film 101 is formed on the silicon substrate 1. Then, the silicon oxide film 101 is patterned. Furthermore, a p-type impurity is implanted using the silicon oxide film 101 as a mask, and the substrate 1 is subjected to annealing. Then the silicon oxide film 101 is removed. Thereby, a first high-concentration isolation diffusion layer 3 is formed.
Next, as shown in FIG. 27, an n-type epitaxial layer 4 is formed on the silicon substrate 1, the buried diffusion layer 2, and the first high-concentration isolation diffusion layer 3 using the epitaxial method.
Next, as shown in FIG. 28, a low-concentration isolation diffusion layer 5a and a p-type well region 5b (see FIG. 24) are selectively and simultaneously formed using photolithography, the implantation of a p-type impurity, and annealing at a high temperature.
Then, in the same manner as the above-described p-type well region 5b, an n-type well region 6 (see FIG. 24) is selectively formed using photolithography, the implantation of a p-type impurity, and annealing at a high temperature.
Next, as shown in FIG. 29, a field insulating film 11 is formed on the prescribed area of the epitaxial layer 4. Then, gate electrodes 7 (see FIG. 24) are formed on the epitaxial layer 4, and n-type diffusion regions 8a, 8b, and 8c are selectively formed in the epitaxial layer 4. Next, p-type diffusion regions 9a, 9b, and 9c are selectively formed in the epitaxial layer 4. Thereby, a p-type diffused resistor element having the p-type diffusion regions 9a is formed in the first island region A, and a bipolar transistor having the n-type diffusion region 8b is formed in the second island region B.
Also at the same time, an NMOS transistor is formed in the p-type well region 5b, and a PMOS transistor is formed in the n-type well region 6 (see FIG. 24). Thus, a CMOS transistor is formed in the third island region C.
However, the recent downsizing of semiconductor devices has inevitably shortened the distance between junctions, and in the operation of circuits, the operation of parasitic transistors induced in junction separation has not been ignored.
In the above-described conventional semiconductor device, the potential of the p-type diffusion region 9a becomes momentarily higher than the potential of the first island region A in the transient state between ON and OFF of Vcc, and current flows from the p-type diffusion region 9a to the first island region A. Thereby the parasitic pnp transistor Q1 that uses the p-type diffusion region 9a as the emitter, the first island region A as the base, and the low-concentration isolation diffusion layer 5a as the collector operates, and current flows into the low-concentration isolation diffusion layer 5a. Here, when the current flows into the low-concentration isolation diffusion layer 5a, the potential of the low-concentration isolation diffusion layer 5a elevates due to the resistance of the low-concentration isolation diffusion layer 5a itself. Due to the elevation of the potential, the parasitic npn transistor Q2 that uses the second island region B as the emitter, the low-concentration isolation diffusion layer 5a as the base, and the first island region A as the collector conducts.
As described above, when parasitic transistors Q1 and Q2 operate, a continuous excessive current flows between the p-type diffusion region 9 and the second island region B. Thus, the problem of a latch-up phenomenon arises.
Similarly in the third island region C shown in FIG. 24, there is a parasitic pnp transistor Q4 that uses the p-type diffusion region 9c, which is the source-drain region of the PMOS transistor, as the emitter, the n-type well region 6 as the base, and the p-type well region 5b as the collector; and there is a parasitic npn transistor Q3 that uses the buried diffusion layer 2 as the collector, the p-type well region 5b as the base, and the n-type well region 8c, which is the source-drain region of the NMOS transistor, as the emitter. In the transient state between ON and OFF of Vcc, current flows from the p-type diffusion region 9 to the n-type well region 6, and the parasitic pnp transistor Q4 operates. Thereby, current flows in the p-type well region 5b, and the potential of the p-type well region 5b elevates. Since the current gain of parasitic bipolar transistors Q3 and Q4 increases at this time, a continuous excessive current flows between (the source-drain region 9c of) the PMOS transistor and (the source-drain region 8c of) NMOS transistor. Thus, the problem of a latch-up phenomenon arises.
Although increase in the distance between the p-type diffusion region 9 and the low-concentration isolation diffusion layer 5a, or increase in the width of the low-concentration isolation diffusion layer 5a is effective to inhibit the operation of the above-described parasitic transistors, any of these goes against the current requirement of downsizing.
Also in a semiconductor device manufactured by the conventional manufacturing method, the concentration gradient of impurities is formed in the junction between the first high-concentration isolation diffusion layer 3 and the low-concentration isolation diffusion layer 5a, and in the junction between the buried diffusion layer 2 and the p-type well region 5b, depending on the thickness and impurity content of the epitaxial layer 4, and on the conditions of heat treatment (temperature, time). Lowering the temperature and reducing the time of heat-treatment to meet the current requirement of downsizing may result in insufficient diffusion of the impurities in the above-described junctions, and may cause a high-resistance layer to be formed in the above-described junctions.
Therefore, the conduction of the above-described parasitic pnp transistor Q1 causes the potential of the low-concentration isolation diffusion layer 5a to elevate easily. Similarly in the third island region C, the conduction of the parasitic pnp transistor Q4 causes the potential of the p-type well region 5b to elevate easily. Thus, the problem of a high possibility of a latch-up phenomenon arises.
Alternatively, a method for lowering the resistance of the above-described junctions can be considered by increasing the impurity content for forming the low-concentration isolation diffusion layer 5a, or by increasing the time for heat treatment after the implantation of impurities. However, since the low-concentration isolation diffusion layer 5a is formed simultaneously with the p-type well region 5b of the NMOS transistor, the driving ability of the NMOS transistor takes precedence. Furthermore, since the low-concentration isolation diffusion layer 5a is formed considering the control of side diffusion to inhibit the isolating width. In other words, since increase in impurity content or heat-treatment time leads to the deterioration of the performance of the NMOS transistor, and to increase in the element area of the bipolar transistor, the problem of going against the improvement of performance by downsizing.